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PRELIMINARY
W150
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
* Maximized electromagnetic interference (EMI) suppression using Cypress's Spread Spectrum technology * Single-chip system frequency synthesizer for Intel(R) 440BX AGPset * Three copies of CPU output * Seven copies of PCI output * One 48-MHz output for USB/one 24-MHz for SIO * Two buffered reference outputs * Two IOAPIC outputs * 17 SDRAM outputs provide support for four DIMMs * Supports frequencies up to 150 MHz * SMBus interface for programming * Power management control inputs Table 1. Mode Input Table Mode 0 1 Input Address FS2 FS1 FS0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Pin 3 PCI_STOP# REF0
Table 2. Pin Selectable Frequency FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CPU_F, 1:2 (MHz) 133.3 124 150 140 105 110 115 120 100 133.3 112 103 66.8 83.3 75 124 PCI_F, 0:5 (MHz) 33.3 (CPU/4) 31 (CPU/4) 37.5 (CPU/4) 35 (CPU/4) 35 (CPU/3) 36.7 (CPU/3) 38.3 (CPU/3) 40 (CPU/3) 33.3 (CPU/3) 44.43 (CPU/3) 37.3 (CPU/3) 34.3 (CPU/3) 33.4 (CPU/2) 41.7 (CPU/2) 37.5 (CPU/2) 41.3 (CPU/3)
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew:............................................. 500 ps SDRAMIN to SDRAM0:15 Delay:.......................... 3.7 ns typ. VDDQ3: ..................................................................... 3.3V5% VDDQ2: ..................................................................... 2.5V5% SDRAM0:15 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.
Logic Block Diagram
VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC REF1/FS2 PLL Ref Freq
Stop Clock Control
Pin Configuration[1]
VDDQ3 REF1/FS2 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI0/FS3 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 SDRAMIN SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 IOAPIC0 IOAPIC_F GND CPU_F CPU1 VDDQ2 CPU2 GND CLK_STOP# SDRAM_F VDDQ3 SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 VDDQ3 24MHz/FS0 48MHz/FS1
I/O Pin Control
CLK_STOP#
VDDQ2 IOAPIC_F IOAPIC0 VDDQ2 CPU_F
W150
PLL 1
/2,3,4
Stop Clock Control
CPU1 CPU2 VDDQ3 PCI_F/MODE PCI0/FS3 PCI1 PCI2 PCI3
Stop Clock Control SDATA SCLK SMBus Logic
PCI4 PCI5 VDDQ3
PLL2
Stop Clock Control
48MHz/FS1 24MHz/FS0 VDDQ3 SDRAM0:15 16 SDRAM_F
Note: 1. 1.Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor.
SDRAMIN
Cypress Semiconductor Corporation Document #: 38-07177 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 27, 2003
PRELIMINARY
Pin Definitions
Pin Name CPU1:2
W150
Pin Type Pin Description O CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. These outputs are affected by the CLK_STOP# input. CPU_F 52 O Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is not affected by the CLK_STOP# input. PCI1:5 11, 12, 13, O PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input 14, 16 interface, see Table 2 and Table 6. These outputs are affected by the PCI_STOP# input. PCI0/FS3 9 I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. PCI_F/MODE 8 I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is not affected by the PCI_STOP# input. When an input, selects function of pin 3 as described in Table 1. CLK_STOP# 47 I CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, affected outputs start beginning with a full clock cycle (2-3 CPU clock latency). IOAPIC_F 54 O Free-running IOAPIC Output: This output is a buffered version of the reference input which is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied to VDDQ2. IOAPIC0 55 O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW. 48MHz/FS1 29 I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be latched, setting output frequencies as described in Table 2. 24MHz/FS0 30 I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched, setting output frequencies as described in Table 2. REF1/FS2 2 I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input will be latched, setting output frequencies as described in Table 2. REF0 3 I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The (PCI_STOP#) PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz). SDRAMIN 17 I Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs (SDRAM0:15, SDRAM_F). SDRAM0:15 44, 43, O Buffered Outputs: These sixteen dedicated outputs provide copies of the signal provided at 41, 40, the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# 39, 38, input is set LOW. 36, 35, 22, 21, 19, 18, 33, 32, 25, 24 SDRAM_F 46 O Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input. SCLK 28 I Clock pin for SMBus circuitry. SDATA 27 I/O Data pin for SMBus circuitry. X1 5 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318 MHz crystal connection or as an external reference frequency input. X2 6 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 1, 7, 15, P Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI 20, 31, output buffers, reference output buffers, and 48-MHz/24-MHz output buffers. Connect to 3.3V. 37, 45 Pin No. 51, 49
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PRELIMINARY
Pin Definitions (continued)
Pin Name VDDQ2 GND
W150
Pin Type Pin Description P Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. 4, 10, 23, G Ground Connections: Connect all ground pins to the common system ground plane. 26, 34, 42, 48, 53 Pin No. 50, 56 resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output (< 40, nominal) is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to minimize system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the corresponding specified output frequency is delivered on the pins, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor 10 k (Load Option 1) W150 Power-on Reset Timer Output Buffer Output Three-state
Q
Overview
The W150 was designed as a single-chip alternative to the standard two-chip Intel 440BX AGPset clock solution. It provides sufficient outputs to support most single-processor, four SDRAM DIMM designs.
Functional Description
I/O Pin Operation Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W150 power-up, the first 2 ms of operation are used for input logic selection. During this period, the five I/O pins (2, 8, 9, 29, 30) are three-stated, allowing the output strapping
Series Termination Resistor Clock Load
Hold Output Low
D
10 k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
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PRELIMINARY
Jumper Options Output Strapping Resistor Series Termination Resistor 10 k W150 Power-on Reset Timer Output Buffer Output Three-state
Q
W150
VDD
R Resistor Value R
Clock Load
Hold Output Low
D
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
Spread Spectrum Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
5 dB/div
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 6. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the SMBus data stream. Refer to Table 7 for more details.
SSFTG
Typical Clock
Amplitude (dB)
-1.0
-0.5% -SS%
0 Frequency Span (MHz)
+0.5% +SS%
+1.0
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
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PRELIMINARY
MAX
W150
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN
Figure 4. Typical Modulation Profile
Serial Data Interface
The W150 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W150 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic Table 3. Serial Data Interface Control Functions Summary Control Function Description
outputs of the chipset. If needed, clock device register changes are normally made upon system initialization. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Operation Data is written to the W150 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4.
Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. For EMI reduction. Production PCB testing. Production PCB testing. No user application. Register bit must be written as 0.
Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. CPU Clock Provides CPU/PCI frequency selections through Frequency Selection software. Frequency is changed in a smooth and controlled fashion. Spread Spectrum Enabling Output Three-state Test Mode (Reserved) Enables or disables spread spectrum clocking. Puts clock output into a high-impedance state. All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 5. Reserved function for future device revision or production device testing.
Table 4. Byte Writing Sequence Byte Sequence 1 Byte Name Bit Sequence Byte Description Commands the W150 to accept the bits in Data Bytes 0-7 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W150 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W150, therefore bit values are ignored ("Don't Care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W150, therefore bit values are ignored ("Don't Care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus.
Slave Address 11010010
2
Command Code
Don't Care
3
Byte Count
Don't Care
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100%
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PRELIMINARY
Table 4. Byte Writing Sequence (continued) Byte Sequence 4 5 6 7 8 9 10 11 Byte Name Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Don't Care Unused by the W150, therefore bit values are ignored (Don't Care). Bit Sequence Byte Description
W150
Refer to Table 5 The data bits in Data Bytes 0-5 set internal W150 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
Writing Data Bytes Each bit in Data Bytes 0-7 control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes 0-7. Table 6 details additional frequency selections that are available through the serial data interface. Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0-5 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 Pin No. - - - - - Pin Name - - - - - Control Function (Reserved) SEL_2 SEL_1 SEL_0 Frequency Table Selection 0 - See Table 6 See Table 6 See Table 6 Frequency Controlled by FS (3:0) Table 2 Frequency Controlled by SEL (3:0) Table 6 Data Byte 0 - 0 0 0 0 0 Bit Control 1 Default
2 1-0
- -
- -
SEL3 Bit 1 0 0 1 1 - - - - Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Bit 0 0 1 0 1
Refer to Table 6 Function (See Table 7 for function details) Normal Operation (Reserved) Spread Spectrum On All Outputs Three-stated - - - - Low Low Low Low - Low Low - - - - Active Active Active Active - Active Active
0 00
Data Byte 1 7 6 5 4 3 2 1 0 7 6 5 - - - - 46 49 51 52 - 8 16 - - - - SDRAM_F CPU2 CPU1 CPU_F - PCI_F PCI5 0 0 0 0 1 1 1 1 0 1 1
Data Byte 2
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PRELIMINARY
Table 5. Data Bytes 0-5 Serial Configuration Map (continued) Affected Pin Bit(s) 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 1 0 - - 29 30 33, 32, 25, 24 22, 21, 19, 18 39, 38, 36, 35 44, 43, 41, 40 - - - - - - - - - - 54 55 - - 2 3 - - 48MHz 24MHz (Reserved) (Reserved) Clock Output Disable Clock Output Disable - - Low Low Low Low Low Low - - Active Active Active Active Active Active Pin No. 14 13 12 11 9 Pin Name PCI4 PCI3 PCI2 PCI1 PCI0 Control Function Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 Low Low Low Low Low Bit Control 1 Active Active Active Active Active
W150
Default 1 1 1 1 1 0 0 1 1 1 1 1 1
SDRAM12:15 Clock Output Disable SDRAM8:11 SDRAM4:7 SDRAM0:3 Clock Output Disable Clock Output Disable Clock Output Disable
Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 - - IOAPIC_F IOAPICO - - REF1 REF0 (Reserved) (Reserved) Disabled Disabled (Reserved) (Reserved) Clock Output Disable Clock Output Disable - - Low Low - - Low Low - - Active Active - - Active Active 0 0 1 1 0 0 1 1 - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0
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PRELIMINARY
Table 6. Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit 3 = 1 Bit 2 SEL_3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit 6 SEL_2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Bit 5 SEL_1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Input Conditions Data Byte 0 Function Normal Operation Test Mode Spread Spectrum Tristate Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU_F, 1:2 Note 2 X1/2 Note 2 Hi-Z PCI_F, PCI0:5 Note 2 CPU/(2 or 3) Note 2 Hi-Z Bit 4 SEL_0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU, SDRAM Clocks (MHz) 133.3 124 150 140 105 110 115 120 100 133.3 112 103 66.8 83.3 75 124 PCI Clocks (MHz) 33.3 (CPU/4) 31 (CPU/4) 37.5 (CPU/4) 35 (CPU/4) 35 (CPU/3) 36.7 (CPU/3) 38.3 (CPU/3) 40 (CPU/3) 33.3 (CPU/3) 44.43 (CPU/3) 37.3 (CPU/3) 34.3 (CPU/3) 33.4 (CPU/2) 41.7 (CPU/2) 37.5 (CPU/2) 41.3 (CPU/3) Output Conditions REF0:1, IOAPIC0,_F 14.318 MHz X1 14.318 MHz Hi-Z 48 MHZ 48 MHz X1/2 48 MHz Hi-Z Output Frequency
W150
Spread On
Spread Percentage 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.9% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.9% Center 0.5% Center 0.5% Center
Table 7. Select Function for Data Byte 0, Bits 0:1
24 MHZ 24 MHz X1/4 24 MHz Hi-Z
Note: 2. CPU and PCI frequency selections are listed in Table 2 and Table 6.
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PRELIMINARY
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description VDD, VIN TSTG TB TA ESDPROT Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
W150
Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min)
Unit V C C C kV
DC Electrical Characteristics (TA = 0C to +70C; VDDQ3 = 3.3V 5%; VDDQ2 = 2.5V 5%)
Parameter Supply Current IDD IDD 3.3V Supply Current 2.5V Supply Current CPU_F, 1:2= 100 MHz Outputs Loaded[4] CPU_F, 1:2= 100 MHz Outputs Loaded[4] GND - 0.3 2.0 320 40 mA mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs VIL VIH IIL IIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current[5] Input High Current[5] Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage Output High Voltage Output Low Current CPU_F, 1:2 PCI_F, PCI1:5 REF0:1 48-MHz 24-MHz SDRAM0:15, _F IOH Output High Current CPU_F, 1:2 PCI_F, PCI1:5 IOAPIC REF0:1 48-MHz 24-MHz IOL = 1 mA IOH = 1 mA CPU_F, 1:2, IOAPIC IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.5V VOH = 1.5V 3.1 2.2 60 96 72 61 60 60 95 43 76 60 50 50 50 73 110 92 71 70 70 110 60 96 90 60 60 60 85 130 110 80 80 80 130 80 120 130 72 72 72 mA mA mA mA mA mA 0.8 VDD + 0.3 -25 10 -5 +5 50 V V A A A A mV V V mA mA mA mA mA mA
Clock Outputs
IOAPIC0, IOAPIC_F VOL = 1.25V
75 95 120 SDRAM0:15, _F VOH = 1.5V Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. All clock outputs loaded with 6" 60 traces with 22-pF capacitors. 5. W150 logic inputs have internal pull-up devices (not to full CMOS level). Logic input FS3 has an internal pull-down device. Document #: 38-07177 Rev. *B Page 9 of 15
PRELIMINARY
DC Electrical Characteristics (TA = 0C to +70C; VDDQ3 = 3.3V 5%; VDDQ2 = 2.5V 5%) (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input threshold Voltage[6] Load Capacitance, Imposed on External Crystal[7] X1 Input Capacitance[8] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 Description Test Condition Min. Typ. Max.
W150
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5%; fXTL = 14.31818 MHz. AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25 Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V 15 5.2 5.0 1 1 45 4 4 55 250 15.5 CPU = 100 MHz 10 3.0 2.8 1 1 45 4 4 55 250 10.5 ns ns ns V/ns V/ns % ps Min. Typ. Max. Min. Typ. Max. Unit
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew
175 3
175 3
ps ms
Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short cycles start) exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 20
Zo
20
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.6/100 MHz Parameter tP tH tL Period High Time Low Time Description Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Min. 30 12.0 12.0 Typ. Max. Unit ns ns ns
tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns Notes: 6. X1 input threshold voltage (typical) is VDDQ3/2. 7. The W150 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
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PRELIMINARY
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued) CPU = 66.6/100 MHz Parameter tF tD tJC Description Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 Min. 1 45 Typ. Max. 4 55 250
W150
Unit V/ns % ps
tSK tO fST
Output Skew CPU to PCI Clock Skew
500 4 3
ps ns ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 15
Zo
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 15
Zo
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter
t P
CPU = 100 MHz Max. 10.5 Unit ns ns ns 4 V/ns 10 3.0 2.0
Description Period High Time Low Time
Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. 15 5.2 5.0 1 4 15.5
tH tL tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
Document #: 38-07177 Rev. *B
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PRELIMINARY
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued) CPU = 66.8 MHz Parameter tF tD tSK tPD Zo Description Output Fall Edge Rate Duty Cycle Output Skew Propagation Delay AC Output Impedance Test Condition/Comments Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising and falling edge at 1.5V Measured from SDRAMIN Average value during switching transition. Used for determining series termination value. 3.7 15 1 45 4 55 250 3.7 15
W150
CPU = 100 MHz Max. 4 55 250 Unit V/ns % ps ns 1 45
Min. Typ. Max. Min. Typ.
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF CPU = 66.8/100 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual PLL Ratio Output Fall Edge Rate Duty Cycle Test Condition/Comments Determined by PLL divider ratio (see m/n below) (14.31818 MHz x 57/34 = 24.004 MHz) 0.5 0.5 45 Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Min. Typ. 24.004 +167 57/34 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Deviation from 24 MHz (24.004 - 24)/24 Output Rise Edge Rate Measured from 0.4V to 2.4V
Frequency Stabilization Assumes full supply voltage reached within 1 ms from from Power-up (cold power-up. Short cycles exist prior to frequency stabilistart) zation. AC Output Impedance Average value during switching transition. Used for determining series termination value. 25
Zo
Ordering Information
Ordering Code W150H W150HT Package Type 56-pin SSOP 56-pin SSOP - Tape and Reel Industrial Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Document #: 38-07177 Rev. *B
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PRELIMINARY
Layout Example
+3.3V Supply FB
VDDQ3
0.005 mF 10 mF
W150
+2.5V Supply FB
VDDQ2
C4 G G G
C3
C1
10 mF
0.005 mf
C2 G G G
G
1 2 3 4 5 6 7 8 9
10
V G
V G
G
G
G V G
G V G G
G G V G G V G
G
G
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
G
G V G
G V G
G
G G
G G
V G
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
G
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) F Cermaic Caps C1 & C3 = 10 - 22 F C2 & C4 = 0.005 G = VIA to GND plane layer V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic
W150
G
G
Document #: 38-07177 Rev. *B
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PRELIMINARY
Package Drawing and Dimensions
56-Lead Shrunk Small Outline Package O56
W150
51-85062-C
Intel is a registered trademark of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07177 Rev. *B
Page 14 of 15
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document History Page
Document Title: W150 440BX AGPset Spread Spectrum Frequency Synthesizer Document Number: 38-07177 REV. ** *A *B ECN NO. 110287 122818 123567 Issue Date 11/13/01 12/22/02 01/28/03 Orig. of Change SZV RBI RGL Description of Change Change from Spec number: 38-00857 to 38-07177 Add Power up Requirements to Maximum Ratings Information Changed the Package Drawing and Dimension to CY standard
W150
Document #: 38-07177 Rev. *B
Page 15 of 15

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